Single-Path Programming on a Chip-Multiprocessor System

In this paper we explore a time-predictable chip-multiprocessor (CMP) system based on single-path programming. To keep the timing constant, even in the case of shared memory access for the CMP cores, the tasks on the cores are synchronized with the time-sliced memory arbitration unit. 1 The Single-Path CMP System The main goal of our approach is to build an architecture that provides a combination of good performance and high temporal predictability. We rely on chip-multiprocessing to achieve the performance goal and on an offline-planning approach to make our system predictable. The idea of the latter is to take as many control decisions as possible before the system is actually run. This reduces the number of branching decisions that need to be taken during system operation, which, in turn, causes a reduction of the number of possible action sequences with possibly different timings that need to be considered when planning respectively evaluating the system’s timely operation.